During their fabrication process, ICs (integrated circuits) often incur defects for various reasons. For that reason, IC devices are usually designed to contain redundant circuit elements, such as spare rows and columns of memory cells in semiconductor memory devices, e.g., a DRAM (dynamic random access memory), an SRAM (static random access memory), or an embedded memory. Such devices are also designed to include particular laser-severable links between electrical contacts of the redundant circuit elements. Such links can be removed, for example, to disconnect a defective memory cell and to substitute a replacement redundant cell. Similar techniques are also used to sever links in order to program or configure logic products, such as gate arrays or ASICs (application-specific integrated circuits). After an IC has been fabricated, its circuit elements are tested for defects, and the locations of defects may be recorded in a database. Combined with positional information regarding the layout of the IC and the location of its circuit elements, a laser-based link processing system can be employed to remove selected links so as to make the IC useful.
Laser-severable links are typically about 0.5-1 microns (μm) thick, about 0.5-1 μm wide, and about 8 μm in length. Circuit element in an IC, and thus links between those elements, are typically arranged in a regular geometric arrangement, such as in regular rows. In a typical row of links, the center-to-center pitch between adjacent links is about 2-3 μm. These dimensions are representative, and are declining as technological advances allow for the fabrication of workpieces with smaller features and the creation of laser processing systems with greater accuracy and smaller focused laser beam spots. Although the most prevalent link materials have been polysilicon and like compositions, memory manufacturers have more recently adopted a variety of more conductive metallic link materials that may include, but are not limited to, aluminum, copper, gold, nickel, titanium, tungsten, platinum, as well as other metals, metal alloys, metal nitrides such as titanium or tantalum nitride, metal silicides such as tungsten silicide, or other metal-like materials.
Conventional laser-based semiconductor link processing systems focus a single pulse of laser output having a pulse width of about 4 to 30 nanoseconds (ns) at each link. The laser beam is incident upon the IC with a footprint or spot size large enough to remove one and only one link at a time. When a laser pulse impinges a polysilicon or metal link positioned above a silicon substrate and between component layers of a passivation layer stack including an overlying passivation layer, which is typically 2000-10,000 angstrom (Å) thick, and an underlying passivation layer, the silicon substrate absorbs a relatively small proportional quantity of infrared (IR) radiation and the passivation layers (silicon dioxide or silicon nitride) are relatively transparent to IR radiation. Infrared (IR) and visible laser wavelengths (e.g., 0.522 μm, 1.047 μm, 1.064 μm, 1.321 μm, and 1.34 μm) have been employed for more than 20 years to remove circuit links.
Laser processing systems have traditionally employed a single laser pulse focused into a small spot for link removal. Banks of links to be removed are typically arranged on the wafer in a straight row, an illustrative one of which is shown in FIG. 1. The row need not be perfectly straight, although typically it is quite straight. The links are processed by the system in a link run 120, which is also referred to as an on-the-fly (“OTF”) run or processing run. During the link run 120, the laser beam is pulsed as a stage positioner continuously passes the row of links across a focused laser spot location 110. The stage typically moves along a single axis at a time and does not stop at each link position. Thus the link run 120 is a processing pass down a row of links in a generally lengthwise direction (horizontally across the page as shown.) Moreover, the lengthwise direction of the link run 120 need not be exactly straight or perpendicular to the lengthwise direction of the individual links that constitute the row, although that is typically approximately true. Impingent upon selected links in the link run 120 is a laser beam whose propagation path is along an axis. The position at which that axis intersects the workpiece continually advances along the link run 120 while pulsing the laser to selectively remove links. The laser is triggered to emit a pulse and sever a link when the wafer and optical components have a relative position such that the pulse energy will impinge upon the link (e.g., when the laser spot 110 matches a trigger position 130). Some of the links are not irradiated and left as unprocessed links 140, while others are irradiated to become severed links 150.
FIG. 2 illustrates a typical link processing system that adjusts the spot position by moving a wafer 240 in an XY plane underneath a stationary optics table 210. The optics table 210 supports a laser 220, a final turn mirror 225, a focusing lens 230, and possibly other optical hardware. The wafer 240 is moved underneath in the XY plane by placing it on a chuck 250 that is carried by a motion stage 260. Alternatively, the wafer 240 can be held still while the optical equipment on the optics table 210 move. As yet another alternative, both the wafer 240 and the optical equipment on the optics table 210 may move to impart a desired relative motion.
FIG. 3A depicts a top view representation of the wafer 240, which includes a number of dies 242. The dies 242 are generally laid out in a regular geometric arrangement. A group of contiguous dies in a typically rectangular pattern constitutes an alignment region 244, at or near the corners of which may be dedicated alignment targets 246. There may be additional alignment targets (not shown) on or near each die. The alignment targets 246 can be used to align the laser beam spot 110 to the wafer 240. Alignment data gathered from the alignment targets 246 in each corner of an alignment region 244 can be used to calculate the positions of links to be processed within each die in the alignment region 244. For example, surface fitting algorithms can be applied to the known corner alignment target data to fit a surface model to the alignment region. This process is sometimes referred to as position geometry correction (PGC).
FIG. 3B is an illustration of link runs across a semiconductor die 242. Both X direction link runs (along the X direction trajectories 310) and Y direction link runs (along the Y direction trajectories 320) are shown. A conventional sequential link blowing process requires scanning the XY motion stage 260 across the wafer 240 once for each link run. Repeatedly scanning back and forth across the wafer 240 results in complete wafer processing. A machine typically scans back and forth processing numerous X-axis link runs 310 before processing a batch of Y-axis link runs 320 (or vice versa). This example is merely illustrative. Other configurations of link runs and processing modalities are possible. For example, link banks and link runs may not be straight rows and may not be processed with continuous motion.
A laser-based link processing system can be employed to remove selected links so as to make the IC useful, as described above, provided positional information regarding the layout of the IC and the location of its circuit elements are known with sufficient accuracy. Because the layout of ideally identical IC wafers can differ slightly from wafer to wafer, it is typically necessary to determine the position of the system's laser beam spot on each wafer by detecting the spot's reflection off identifiable features on the wafer and thereby calibrating the laser system's coordinate space to those features before processing can begin. Such positional calibration processes have historically been practiced in single-beam laser-based link processing systems.